This invention relates generally to integrated circuit (IC) processes and fabrication, and more particularly, to copper interconnection structures, and a method of forming copper interconnection structures, without intervening contamination barrier layers, to improve electrical conductivity between the copper levels.
The demand for progressively smaller, less expensive, and more powerful electronic products, in turn, fuels the need for smaller geometry integrated circuits, and large substrates. It also creates a demand for a denser packaging of circuits onto IC substrates. The desire for smaller geometry IC circuits requires that the interconnections between components and dielectric layers be as small as possible. Therefore, research continues into reducing the width of via interconnects and connecting lines. The conductivity of the interconnects is reduced as the surface area of the interconnect is reduced, and the resulting increase in interconnect resistivity has become an obstacle in IC design. Conductors having high resistivity create conduction paths with high impedance and large propagation delays. These problems result in unreliable signal timing, unreliable voltage levels, and lengthy signal delays between components in the IC. Propagation discontinuities also result from intersecting conduction surfaces that are poorly connected, or from the joining of conductors having highly different impedance characteristics.
There is a need for interconnects and vias to have both low resistivity, and the ability to withstand volatile process environments. Aluminum and tungsten metals are often used in the production of integrated circuits for making interconnections, or vias, between electrically active areas. These metals are popular because they are easy to use in a production environment, unlike copper which requires special handling.
Copper (Cu) is a natural choice to replace aluminum in the effort to reduce the size of lines and vias in an electrical circuit. The conductivity of copper is approximately twice that of aluminum, and over three times that of tungsten. As a result, the same current can be carried through a copper line having half the width of an aluminum line.
The electromigration characteristics of copper are also much superior to those of aluminum. Aluminum is approximately ten times more susceptible than copper to degradation and breakage through electromigration. As a result, a copper line, even one having a much smaller cross-section than an aluminum line, is better able to maintain electrical integrity.
There have been problems associated with the use of copper, however, in IC processing. Copper contaminates many of the materials used in IC processes and, therefore, care must be taken to keep copper from migrating. Various means have been suggested to deal with the problem of copper diffusion into integrated circuit material. Several materials, particularly refractory metals, have been suggested for use as barriers to prevent the copper diffusion process. Tungsten, molybdenum, and titanium nitride (TiN) are examples of refractory metals which may be suitable for use as copper diffusion barriers. However, the adhesion of copper to these diffusion barrier materials has been an IC process problem, and the electrical conductivity of such materials is an issue in building IC interconnects.
Metal cannot be deposited onto substrates, or into vias, using conventional metal deposition processes, such as sputtering, when the geometries of the selected IC features are small. It is impractical to sputter metal, either aluminum or copper, to fill small diameter vias, since the gap filling capability is poor. To deposit copper, various chemical vapor deposition (CVD) techniques are under development in the industry.
In a typical CVD process, copper is combined with an organic ligand to make a volatile copper compound or precursor. That is, copper is incorporated into a compound that is easily vaporized into a gas. Selected surfaces of an integrated circuit, such as diffusion barrier material, are exposed to the copper containing gas in an elevated temperature environment. When the volatile copper gas compound decomposes, copper is left behind on the heated selected surface. Several copper compounds are available for use with the CVD process. It is generally accepted that the molecular structure of the copper compound, at least partially, affects the conductivity of the copper film residue on the selected surface.
Connections between metal levels, such as copper, which are separated by dielectric interlevels, are typically formed with a damascene method of via formation between metal levels. The underlying copper film is first completely covered with the dielectric, a typical dielectric is silicon dioxide. A patterned photoresist profile is then formed over the dielectric, and an interconnection trench is etched into the dielectric. Another layer of resist has an opening, or hole, in the photoresist overlying the trench, corresponding to the area in the dielectric where the via is to be formed. The dielectric not covered with photoresist is then etched to remove oxide underlying the hole in the photoresist. The photoresist is then stripped away. A thin film of copper, or some other metallic material, is then used to fill the via and trench. A layer consisting of dielectric with a copper via through it now overlies the copper film. The excess copper remaining is removed with a chemical mechanical polish (CMP) process, as is well known in the art. The result is an "inlaid", or damascene, structure.
The formation of copper interconnects requires the copper lines be completely surrounded with barrier layers. The barrier layers can be either conductive or non-conductive. Additional process steps are required in the fabrication process to protect existing barrier layers from etching and to prepare these barrier layers surfaces to adhere to copper and other IC materials. Conductive barriers must also be prepared to have a good electrical interface with metal levels. Barrier layers may be deposited as a film between the various metal levels and dielectric interlevels of the IC. The damascene process may require the formation of additional barrier layers during the formation of a damascene via and trench. Most, preexisting, conductive barrier layers degrade conductance between the copper via and metal levels, but these barriers are often difficult to remove. Procedures have been developed to minimize the resistance between a copper via and an interfacing conductive barrier layer. In addition, compromises are often made between adhesion and conduction characteristics.
A co-pending application, Ser. No. 08/717,267, filed Sep. 20, 1996, entitled, "Oxidized Diffusion Barrier Surface for the Adherence of Copper and Method for Same", invented by Nguyen et al., Attorney Docket No. SMT 123, which is assigned to the same Assignees as the instant patent, discloses a method for oxidizing the diffusion barrier surface to improve the adherence of copper to a diffusion barrier. In low speed electrical circuits the resistance offered by a thin level of oxide is unnoticeable. However, in higher speed applications even a small amount of resistance can increase the propagation delay of electron current across an oxide layer. The primary purpose of this, above mentioned, patent application is to improve the ability of copper to remain deposited on a surface, not on improving the conductivity between copper and another surface.
Another co-pending application, Ser. No. 08/717,315, filed Sep. 20, 1996, entitled, "Copper Adhered to a Diffusion Barrier Surface and Method for Same", invented by Charneski and Nguyen, Attorney Docket No. SMT 243, which is assigned to the same Assignees as the instant patent, discloses a method for using a variety of reactive gas species to improve copper adhesion without forming an oxide layer over the diffusion barrier. However, the focus of this patent is to improve copper adhesion, not to improve the conductivity of copper deposited on a surface.
Another co-pending application, Ser. No. 08/729,567, filed Oct. 11, 1996, entitled, "Chemical Vapor Deposition of Copper on an ION Prepared Conductive Surface and Method for Same," invented by Nguyen and Maa, Attorney Docket No. 114, which is assigned to the same Assignees as the instant patent, discloses a method of preparing a conductive surface, such as a barrier layer, with an exposure to the ions of an inert gas to improve electrical conductivity between a conductive surface and a subsequent deposition of copper. However, the primary purpose of this invention is to prepare a conductive surface that is substantially free of by-products and IC process debris.
Tsuchiya et al., in the article "Ultra-Low Resistance Direct Contact Cu Via Technology Using In-Situ Chemical Vapor Cleaning", 1997 Symposium on VSLI Technology Digest of Technical Papers, pg. 59-60, disclose a method forming a dual damascene direct connection between two copper levels. The connection is formed through two dielectric layers to an underlying copper levels, with barrier layers between the three levels. However, no method is disclosed for forming a via connection between metal levels without an intervening barrier layer. Neither is a method disclosed for forming a dual damascene connection through a single dielectric interlevel when barrier layers must be fabricated for the interconnection trench.
It would be advantageous to employ a method of minimizing the resistance between a copper via and an interfacing metal level in an IC.
It would be advantageous to employ a means of selectively forming barrier layers in a via or damascene structure to eliminate the poorly conductant interfaces between copper and conductive barrier layers.
It would be advantageous to employ a method of selectively depositing and selectively etching barrier layers in the formation of a via or damascene structure. Further, it would be advantageous if the method reduced the number of process steps, and improved the conductivity between metal levels.
It would be advantageous to employ a method of selectively forming barrier layers in an IC interconnect to prevent copper contamination, and selectively removing barrier layers to enhance conductivity between copper levels.
Accordingly, in an integrated circuit including a first metal horizontal level, a first barrier layer overlying the first metal level, a first dielectric interlevel overlying the first barrier layer, and a second barrier layer overlying the first dielectric interlevel, a method is provided for forming a low resistance interconnect between metal levels comprising the following steps:
a) etching selected overlying areas of the first barrier layer, the first dielectric interlevel, and the second barrier layer to form a via, exposing vertical sidewall surfaces of the first dielectric interlevel and selected areas of the first metal level; PA1 b) conformally depositing a third barrier layer over the vertical sidewall surfaces of the first dielectric interlevel and the first metal level selected areas exposed in step a); and PA1 c) anisotropically etching, in the horizontal direction, to selectively remove the third barrier layer deposited over the first metal level selected areas, but not the vertical sidewall surfaces of the first dielectric interlevel. A via, having barrier surface sidewalls, is prepared to directly connect the first metal level with a subsequently deposited metal level. PA1 a) etching selected areas of the first dielectric interlevel second thickness, forming a damascene interconnection trench, and exposing vertical sidewall surfaces of the first dielectric interlevel second thickness and selected horizontal surfaces of the first dielectric interlevel first thickness; PA1 b) anisotropically depositing, in a horizontal direction, a second barrier layer over the first dielectric interlevel, to overlie the selected horizontal surfaces of the first dielectric interlevel first thickness exposed in step a), and minimally cover the vertical sidewall surfaces of the first dielectric interlevel second thickness; PA1 c) etching selected overlying surfaces of the second barrier layer deposited in step b), selected horizontal surfaces of the first dielectric interlevel first thickness, and the first barrier level, exposing vertical sidewall surfaces of the first dielectric interlevel first thickness and selected areas of the first metal level, whereby a via is formed from the trench to the first metal level selected areas; PA1 d) conformally depositing a third barrier layer over the vertical sidewall surfaces of the first dielectric interlevel second thickness exposed in step a), the second barrier layer deposited in step b), and the first metal level selected areas and vertical sidewall surfaces of the first dielectric interlevel first thickness exposed in step c); and PA1 e) anisotropically etching, in the horizontal direction, to selectively remove the third barrier layer overlying the first metal level selected areas, but not the third barrier layer overlying the vertical sidewall surfaces of the first dielectric interlevel first and second thicknesses. A damascene process via and trench, having barrier sidewall surfaces, are prepared to directly connect the first metal level with a subsequently deposited metal level.
Also provided, in an integrated circuit (IC), is a low resistance metal level via interconnection comprising a metal level, a dielectric interlevel overlying the first metal level, and a via through selected areas of the dielectric interlevel, exposing sidewall surfaces of the dielectric interlevel and selected areas of the metal level. The via interconnection further comprises a barrier layer over the sidewall surfaces of the dielectric interlevel, formed by conformally depositing barrier layer material over the sidewall surfaces of the dielectric interlevel and the metal level selected areas, and anisotropically etching, to selectively remove the barrier layer over the metal level selected areas. A via, having barrier surface sidewalls, is prepared to directly connect the metal level with a subsequently deposited metal level.
In an integrated circuit including a first metal horizontal level, a first barrier layer overlying of the first metal level, and a first dielectric interlevel overlying the first barrier layer, the first dielectric interlevel having a first thickness and a second thickness overlying the first thickness, a method is provided for forming a low resistance dual damascene interconnect between metal levels comprising the following steps:
Also provided, in an integrated circuit (IC), is a low resistance metal level dual damascene interconnection comprising a horizontal metal level, a dielectric interlevel overlying the metal level, the dielectric interlevel having a first thickness and a second thickness overlying the first thickness. The damascene interconnection further comprises a damascene interconnection trench formed through selected areas of the dielectric interlevel second thickness, exposing vertical sidewall surfaces of the dielectric interlevel second thickness and selected horizontal surfaces of the dielectric interlevel first thickness. In addition, the damascene interconnection comprises an insulating barrier layer formed by anisotropically deposition, in a horizontal direction, to overlie the selected horizontal surfaces of the dielectric interlevel first thickness.
The damascene interconnection comprises a via through selected overlying areas of the insulating barrier layer, and the first dielectric interlevel first thickness, exposing sidewall surfaces of the dielectric interlevel first thickness and selected areas of the metal level. Finally, the damascene interconnection comprises a conductive barrier layer formed by conformally depositing the conductive barrier layer material over the sidewall surfaces of the first dielectric interlevel first and second thicknesses, the selected horizontal surfaces of the dielectric interlevel first thickness, and the metal level selected areas. Then, the conductive barrier is anisotropically etched, in the horizontal direction, to selectively remove the conductive barrier layer deposited over the metal level selected areas. The damascene process via and trench, having conductive barrier surface sidewalls, are prepared to directly connect the metal level with a subsequently deposited metal level.